A MIM capacitor can be considered as a trench-type parasitic capacitor with an insulator layer disposed between two metal layers. A conventional connection (strap) interface between a deep trench (DT) MIM capacitor and an adjacent transistor, e.g., a planar field effect transistor (FET) or a FinFET, typically suffers from having a high resistance due at least to the area of the strap. The high interface resistance can detrimentally affect performance, such as when the DT MIM capacitor is used in a dynamic random access memory (DRAM) application such as an embedded DRAM (eDRAM) application.